Integrated circuit (“IC”) design consists of a number of steps. Typically, the design starts with a specification of the functional performance characteristics of the IC. The IC is then typically broken down into more manageable blocks so that the blocks may be divided among multiple designers and analyzed in pieces by computer aided design tools. Next, logic designers write register transfer level (“RTL”) descriptions of each block. Next, floor plans are created for each of the blocks. After verifying that the RTL descriptions are accurate, the designers estimate the size of each block. Then designers create a floor plan that describes the relative placement of the blocks on the IC. Finally, the designers layout the actual circuits of each block.
One of the most difficult challenges for a designer is laying out the circuit so that the circuit meets timing constraints. Without a systematic approach, designers resort to continually simulating and modifying the design to achieve the timing constraints.
One way to assist designers in meeting timing criteria is provided by a method of logical effort. The method of logical effort is a simple way to estimate delay in a complementary metal oxide semiconductor (“CMOS”) circuit. The method can also be utilized to determine the proper number of logic stages on a path and the best transistor sizes for the logic gates.
According to the method of logical effort, the delay incurred by a logic gate is comprised of two components. The first component is known as “parasitic delay.” The second component, known as “effort delay,” is proportional to the load on the logic gate's output. The effort delay is equal to the “logical effort” multiplied by the “electrical effort.” As discussed below, logical effort characterizes the properties of the logic gates and electrical effort characterizes the load.
Logical effort is a unitless parameter defined so that an inverter has a logical effort of one. The logical effort of several common gates, assuming a beta ratio (pull-up transistor width/pull-down transistor width) of 2, is shown in the following table:
Number of InputsGate type12345nInverter1NAND4/35/36/3 7/3 (n + 2)/3NOR5/37/39/311/3(2n + 1)/3Multiplexer2 2 222XOR (parity)41232
In general, the logical effort of a logic element describes how much worse the logic gate is at driving an output load when compared to an inverter. Accordingly, the logical effort of a gate indicates how much more slowly the logic gate will drive a load than would an inverter.
The electrical effort can be defined as the ratio of the capacitance that loads the output of the logic gate divided by the capacitance presented by the input terminal of the logic gate.
In summary, the effort delay incurred by a logic gate can be stated as:effort delay=(logical effort)(electrical effort)+parasitic delay
The method of logical effort analysis is described more completely in Logical Effort: Designing Fast CMOS Circuits, by Ivan Sutherland, Bob Sproull, and David Harris, Morgan Kaufman Publishers, Inc. (1999), ISBN # 1-55860-557-6.